A makefile is a list of commands and their dependencies. This makefile will have two commands: all and clean.
The makefile command's first line will state command's name and dependencies. The second will issue the commands. The second must be prefixed by a tab.
For each dependency, it looks up another command. Example: were there a file.o
dependency, it would look up a file.o
command, but if it can't be found it looks for an file named file.o
.
%
before text will specify a wildcard. The command %o: %.c
matches any command ending with a o
and its dependencies are any file ending with a c
. main.o
would match.
$<
specifies whatever was the dependency. So in all: main.c
, $<
would refer to main.c.
At the top of the file the key values are the constants in the file. They are accessed via $(NAME)
later.
OBJS=main.o
CFLAGS=-O3
LIBS=
PROG=main
all:$(OBJS)
gcc -o $(PROG) $(LIBS) $(OBJS)
%o:%c
gcc $(CFLAGS) -c $<
clean:
rm -rf $(PROG) $(OBJS)